library ieee;
use ieee.std_logic_1164.all;

-- This arbitrary state machine is probably not very useful in reality, but demonstrates 

entity mux4to1 is
    port (d0,d1,d2,d3         : in  std_logic_vector(30 downto 0);
          q                   : out std_logic_vector(30 downto 0);
          sel                 : in  std_logic_vector(1 downto 0)
    );
end mux4to1;

architecture behavior of mux4to1 is

begin

process(sel,d0,d1,d2,d3)
	begin
	case sel is
		when "00" =>
		    q <= d0;
		when "01" => 
			q <= d1;
		when "10" =>
			q <= d2;
		when "11" =>
			q <= d3;
	end case;
end process;

end behavior;